The present invention relates to a method of fabricating a nonvolatile semiconductor memory device, and particularly relates to a method of fabricating an electrically erasable nonvolatile semiconductor memory device such as a large capacity EPROM device, EEPROM device and flash memory device.
Conventional fabrication methods of nonvolatile semiconductor memory devices are described in Japanese Patent Laid-Open Publication No. Hei 5-251712 (referred to as the first conventional example hereafter) or Japanese Patent Publication No. 2515715 (referred to as the second conventional example hereafter).
Conventional fabrication methods of nonvolatile semiconductor memory devices are explained below by referring to the figures.
FIG. 7A to FIG. 7C and FIG. 8 are cross sectional views which show a process sequence for conventional fabrication methods of nonvolatile semiconductor memory devices.
First, as shown in FIG. 7A, a p-type well 101a is formed on a semiconductor substrate 101 composed of p-type silicon, and then, an element isolation insulation film 102 (hereinafter referred to as insulation film) is selectively formed thereon. Then, a tunnel oxide film 103, a first poly-silicon film 104A, a capacitive insulation film 105 and a second poly-silicon film 106A that has about 300 nm film thickness are sequentially deposited on element forming regions on the semiconductor substrate 101.
Then, as shown in FIG. 7B, a plurality of gate structures 107 are obtained by applying patterning to the second poly-silicon film 106A, the capacitive insulation film 105, the first poly-silicon film 104A and the tunnel oxide film 103 to form a floating gate electrode 104B from the first poly-silicon layer 104A and a floating gate electrode 104B from the second poly-silicon film 106A.
Next, as shown in FIG. 7C, a thermal oxidation silicon film 110 is formed on the entire surface of the semiconductor substrate 101, which includes the insulation films 102 and the gate structures 107, by using a thermal oxidation method. Then, by using a CVD method, an insulative side wall spacer 111 composed of silicon oxide is formed on the side surfaces of the gate structures 107 by depositing a silicon oxide film on the entire surface of the thermal oxidation silicon film 110 and by performing anisotropic etching on the deposited silicon oxide film. Here, in the first conventional example, although the film thickness of the insulative side wall spacer 111 in the direction parallel to the substrate surface is not shown the film thickness must be at least 60 nm considering that a purpose is to prevent injected ions from entering the floating gate electrode 104B when arsenic ions are injected during later processes. In the second conventional example, the film thickness of the insulative side wall spacer is set to 500 nm.
Then, an ion injection layer 112A is formed by injecting arsenic ions into the p-type well 101a with an acceleration energy of 70 keV to 90 keV and dosage of about 1×1016 cm−2 by using each insulative side wall spacer 111 and each gate structure 107 as masks.
Next, as shown in FIG. 8, a source diffusion layer 112B and a drain diffusion layer 112C are formed by scattering arsenic ions in the ion injection layer 112A to lower portions of the side surface of the gate structure 107, that is, to end portions of the channel region by heat treating the semiconductor substrate 101.
In this way, according to the first conventional example and the second conventional example, because the thermal oxidation silicon film 110 formed on the side surfaces of the gate structure 107 and located beside the gate structure 107 are covered by the insulative side wall spacer 111 having a relatively large film thickness, arsenic ions hardly reach the thermal oxidation silicon film 110 on the side surfaces of the floating gate electrode 104B in particular. Consequently, because insulation performance of the thermal oxidation silicon film 110 on the side surfaces thereof is not lowered, data retention characteristic of memory cells can be improved.
However, in the above described conventional fabrication methods of nonvolatile semiconductor memory devices, if the film thickness of the insulative side wall spacer 111 is relatively large compared to that of the gate structure 107, the distance between the end portion of the ion injection layer 112A and the channel region is increased, so that an extended period of time is required for heat treatment to diffuse injected ions.
If, a MOS type semiconductor device that controls a nonvolatile semiconductor memory device or a micro controller that requires high speed operation or a MOS type semiconductor device for micro processor, is formed on the same substance, this extended period of time of heat treatment adversely affects various impurity concentrations such as channel impurity of a MOS type transistor.
Specifically, it is often the case that MOS type transistor gate electrodes that are used to construct a micro controller or a micro processor described above adopt dual gate or polycide gate structure. For this reason, if heat treatment is applied to dual gates or polycide gates for a long period of time, boron (B) ions may diffuse out of P+ type poly-silicon which is used to construct the gates, and silicide may peel off or channel shorting effect of MOS type transistor may become exaggerated. Therefore, because the recent CMOS technology, which requires high performance and miniaturization, tries to reduce thermal hysteresis to as small as possible, if this trend continues, a problem is generated that it would be difficult to form miniaturized CMOS circuits with high performance and nonvolatile semiconductor memory devices on the same substrate.
Furthermore, although not shown in the figures, sufficiently thick film of an insulative side wall spacer 111 can not be formed on the side surface of insulation film 102, where the step portion of the insulation film 102 is smaller than the gate structure 107 on the semiconductor substrate 101. For this reason, a long period of heat diffusion process causes injected impurity ions to diffuse to the bottom portion of the insulation film 102 from both sides so that the insulation characteristic of the insulation film 102 is degraded. This generates a problem that the insulation film 102 cannot be miniaturized.
On the other hand, if a sufficiently thick film of an insulative side wall spacer 111 is made to form on the insulation film 102, then, the area of an ion injection layer 112A is reduced, thus, the gate width must be widened. In this case, also, it is difficult to miniaturize the insulation film 102.
Also, if the distance between the adjacent gate structures 107 is reduced in order to highly integrate a nonvolatile semiconductor memory device, an insulative side wall spacer 111 having a film thickness larger than one half of this distance, can not be implemented.
Furthermore, in the conventional fabrication method, if the film thickness of the insulative side wall spacer 111 is reduced too much, a problem is generated that injected arsenic ions cause damage to the thermal oxidation silicon film 110 formed on the side surfaces of the gate structure 107 and located beside the gate structure 107.